Low Power Area Efficient Pulse Triggered Flip-Flop Design Based On A Signal Feed Through Scheme

Authors:MOGILI REKHA, V.MADHAVA SWAMY, D.SUDHAKAR3, DR. D.NAGESWAR RAO

0316-0321

Implementation of UART with BIST Technique in FPGA

Authors:K. SHIVA KRISHNA, GOLLA RAMESH, MOHAMMED JAVEED

0322-0327

VLSI Implementation of Delayed LMS Adaptive Filter with Efficient Area-Power-Delay

Authors:JASMINE RACHEL VASALA, MOHAMMED JAVEED, GOLLA RAMESH

0328-0332

Data Encoding Techniques for Reducing Energy & Lower Power Dissipation in Network on Chip

Authors:NAZIA SAMREEN, MOHAMMED JAVEED, GOLLA RAMESH

0333-0338

FPGA-Based Advanced Traffic Light Controller Simulation

Authors:BANDI SWAPNA, MOHAMMED JAVEED, GOLLA RAMESH

0339-0341

Adaptive Design of High Speed Multiplier using Sequential Circuits And Reversible Logic

Authors:METHUKU SRIVIDYA, MOHAMMED JAVEED, GOLLA RAMESH

0342-0345

FPGA Realization of Radix-4 Booth Multiplication Algorithm for High Speed Arithmetic Logics

Authors:MINHAZ SULTANA, V. KARTHIK

0346-0351